OSA 5420 series mid-scale Syncjack PTP Grandmaster synchronisation distribution and assurance devices

The OSA 5420 series mid-scale Syncjack PTP Grandmaster synchronisation distribution and assurance devices can be utilised in a variety of network synchronisation applications. These include IEEE 1588v2 Grandmaster, Boundary Clock, Slave Clock and Assisted Partial Timing Support (APTS).

The built-in global navigation satellite system (GNSS) receiver and primary reference time clock (PRTC) capability, together with the redundant power supply option, make the series suitable for synchronisation delivery.

Timing can be easily distributed and assured throughout a network over existing packet infrastructure. In addition to packet-based timing, the product also scales for bulk delivery of legacy frequency synchronisation signals, as well as next-generation phase and frequency synchronisation signals. Expansion slots for BITS and 1PPS/ToD fan-out modules make the device suitable for physical timing distribution applications at the edge of the network.

The product is designed to deliver the phase and frequency information required by next-generation network technologies including LTE-A, LTE-TDD, enterprise networks and financial data centres. The latest ITU-T PTP telecom profiles for frequency and time/phase delivery are supported, as well as the latest PTP Enterprise profile.

The product enables continuous monitoring of timing performance while in service, raising an alarm if needed. It gives mobile and wireline network operators a valuable approach to timing distribution. It enables them to efficiently distribute timing from the network edge and ensure that base station clocks precisely track their master.

Features include technology for timing distribution, monitoring and testing; precise IEEE 1588v2 PTP frequency and phase synchronisation to radio access networks; built-in GNSS receiver and Grandmaster clock functionality; extended holdover performance including high-end quartz and rubidium oscillator options; operation in Grandmaster, APTS, Boundary and Slave Clock modes; scalable fan-out of multiple physical synchronisation output interfaces; and high-availability design including APTS clock selection, automatic asymmetric delay compensation and power supply redundancy.